The present invention relates to radio transmission systems, and more particularly to a digital radio transmission system that simplifies circuitry for forward error correcting encoders and reduces the period of switching between regular and standby channels in the event of a fault due to fading.
With advancing technologies in digital radio transmission, multilevel quadrature amplitude modulation techniques such as 16 QAM and 64 QAM are increasingly incorporated into microwave digital radio transmission links which interconnect digital switching nodes. To improve the bit error rate of the radio transmission facilities forward error correction techniques are employed. Specifically, the conventional digital microwave radio transmission system comprises a bipolar-to-unipolar converter for converting the bipolar time-division digital signals transmitted over coaxial cables from a switching node to unipolar TDM digital signals and a transmit digital processing unit which performs time expansion on a block of a prescribed number of the incoming data bits and inserts additional bits for channel supervision and switching to form a series of composite bits for transmission to a receiving station where processes the signal in a manner inverse to that of the transmitting station. To effect forward error correction in the transmitting station, the composite bits are fed to a forward error correcting encoder where the composite bits are again time-compressed to leave a time slot and error computations are performed on the time-compressed composite bits according to an error encoding theorem to generate an error correcting code which is inserted to the time slot to form a block code. The error decoding process at the receiving station is a process inverse to that the error encoding process and two stages of time expansion are required for expanding the time scale of the composite bits following the execution of an error decoding process and for expanding the time scale of the compressed data bits after extraction of the additional bits.
Since the time compression process requires a memory, a phase-locked loop and a counter for matching different data rates, they must be duplicated for insertion of control bits and insertion of error correcting codes. Likewise, the time expansion process requires a similar arrangement, and therefore phase-locked loops and counters must be duplicated for the error correcting decoder and receive digital processing unit, although such duplications serve to minimize the timing disruption in the sequence of computations of the forward error correcting encoder if channel switching is effected at a point between the output of a regular-channel transmit digital processing unit and the input of a standby-channel forward error correcting encoder in the event of a fault in the regular channel.